Overlay performance at the Back-End-Of-The-Line (BEOL) portion of integrated circuit fabrication is critical. Improper alignment of successively laid masks can lead to defective wafers. The increasingly smaller size of integrated circuits further complicates the process. Overlay shift error induced by metal deposition and Chemical-Mechanical Polishing (CMP) is of particular concern.
FIG. 1A shows the objective of the process. Four trenches etched in an oxide layer of a semiconductor wafer form the edges of a box. At a later point in the manufacture, four ridges of a metal layer will form a similar pattern to be situated within the oxide pattern. Unfortunately, current methods result in this configuration being misaligned by overlay shift.
FIG. 1B shows a cross-sectional view of the wafer in FIG. 1a in the various stages of manufacture. Trenches 12 and 13 are etched into oxide layer 10. A first metal layer 14, usually tungsten, is deposited over the surface. The tungsten layer 14 undergoes a CMP process, which leaves the tungsten remaining in trenches 12 and 13 asymmetrical in profile. FIG. 2 shows that the rotation pattern of a polishing apparatus makes it difficult to achieve a truly symmetric result. This is the first source of error in the overlay alignment.
Referring again to FIG. 1B, a second metal layer 16 is then deposited over the surface. The irregular contour of the tungsten layer 14 in trenches 12 and 13 is amplified by the metal layer 16, and the shift error is increased. FIG. 2 again shows that the technique of using plasma vapor deposition (PVD) of the metal layer creates irregularities. Referring again to FIG. 1B, a photoresist layer pattern 18 and 19 is deposited on the metal layer 16 in the desired configuration. It is aligned using the first pattern in the oxide 10, which is now shifted. When the metal layer 16 is etched according to the photoresist pattern 18 and 19, the result is a misalignment of the two box configurations.
The problem can affect wafer yield due in part to the Advanced Process Control (APC) algorithm used for batch production. As shown in FIG. 3A, a pilot run is done on a wafer by aligning the photoresist material after the second metal deposition, as discussed above. The data from the pilot run is then used to align the photoresist material on all subsequent wafers, with a ΔSx and ΔSy factored in to account for overlay shift.
This is an arduous task. ΔSx and ΔSy can vary in value, depending on metal layer target lifetime and the chamber and tools used. A very complex APC and photo running mode are also required to achieve an acceptable overlay. It is therefore desirable to use a method which overcomes the induced overlay shift without being impacted by variations in process, tools used, or time. It is also desirable to use a method which avoids a complex APC system for overlay control, and creates an improvement in total wafer yield. It is also desirable to utilize a method which does not carry prohibitive cost and does not require extra process steps.